National Institute for Nuclear Physics in Italy Adopts AMD EPYC™ Processor for Future Research Efforts
AMD EPYC 7000 Series Processor Wins Praise for its High-Performance and Advanced Features
SANTA CLARA, Calif., June 25, 2018 (GLOBE NEWSWIRE) -- AMD today announced The National Institute for Nuclear Physics (INFN) in Italy has picked the AMD EPYC 7351 processor to power its high-performance computing cluster. INFN, a leading European research institution, conducts theoretical and experimental research in the fields of subnuclear, nuclear, and astroparticle physics while offering access to its exceptional processing resources across Europe.
“As a tier one provider of clustered compute and storage for the largest currently ongoing experiments in physics, INFN delivers access to the massive amount of processing required for advanced research in nuclear physics,” said Luca dell’Agnello, head of the tier one center, INFN. “With the adoption of AMD EPYC into the institute, we are offering the latest generation of processing capability to our users and expanding the overall compute capabilities.”
The 16-core AMD EPYC 7351 provides the full complement of 128 lanes of PCIe connectivity and eight memory channels available on all EPYC 7000-series processors.
“We are extremely proud to have the high-performance AMD EPYC processor selected for the INFN datacenter,” said Scott Aylor, corporate vice president and general manager of Datacenter Products, AMD. “High-performance computing is another environment where the AMD EPYC processor feature set stands out for its ability to deliver scalable support for the compute and storage resources required for advanced research.”
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1 A single AMD EPYC™ 7601 processor offers up to 2TB/processor (x 2 = 4TB), versus a single Xeon Platinum 8180 processor at 768Gb/processor (x 2 = 1.54TB). NAP-44
2 AMD EPYC™ processor supports up to 128 PCIe® Gen 3 I/O lanes (in both 1 and 2-socket configuration), versus the Intel® Xeon® SP Series processor supporting a maximum of 48 lanes PCIe® Gen 3 per CPU, plus 20 lanes in the chipset (max of 68 lanes on 1 socket and 116 lanes on 2 socket). NAP-56
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