DesignCon Unveils 2025 Award Winners for Best Paper Awards and Engineer of the Year
SANTA CLARA, CA / ACCESS Newswire / March 6, 2025 /DesignCon, the premiere event for chip, board and systems design engineers, announces the 2025 Engineer of the Year, honoring excellence in engineering and new product advancements at the chip, board or system level and the winners of the prestigious 2025 Best Paper Award, recognizing exceptional contributions to the educational goals of the DesignCon program.
The 2025 DesignCon "Engineer of the Year" is Ben Dannan, founder and chief technologist, Signal Edge Solutions,a service dedicated to bridging the gap between signal integrity, a measure of the quality of an electrical signal, and power integrity, electronic engineering efforts aimed at ensuring that power supply subsystems support the performance of an entire electronic system. Before starting Signal Edge Solutions, Dannan spent time at Northrop Grumman, Bosch Security Systems and Diversey. Dannan has strong ties to DesignCon as Technical Program Committee member, Best Paper Award Winner in 2024 and 2020 and 40 Under 40 winner in 2024.
"For 30 years, DesignCon has been the premier event where we celebrate both the cutting-edge innovations shaping our future and the exceptional contributions that have brought us to where we are today," says Suzanne Deffree, Group Event Director, Informa Markets Engineering. "All recipients push the boundaries of what 's possible and inspire the next generation of engineers. The dedication and innovative spirit of professionals are the driving forces behind the advancements that define our industry and fuel the progress of modern technology."
DesignCon Best Paper Awards honor outstanding contributions to the educational goals of the DesignCon program and acknowledge the authors as leading practitioners in semiconductor and electronic design.
The 2025 Best Paper Winners:
400G+ Electrical Pathfinding, authors from AMD.
Balancing Current Density to High-Power ASICs in Lateral Power Delivery Designs, Brian Hostetler, HPE Inc.
Beyond 200G: Brick Walls of 400G Links per Lane, authors from Samtec,University of L 'Aquila and Keysight Technologies.
Foundational Model Approach for SI/PI Analysis Using Large Language Model Techniques, authors from Hewlett Packard Enterprise.
Low Latency Speculative Error Correction Using Simplified ML Detector for 64Gbps Wireline Transceiver, authors from Cadence Design Systems.
Next Generation 224 Gbps-PAM4 Linear: Host TX/RX, Electrical/Optical Channel Characteristics, and End-to-End Link Simulation and Analysis, authors from Intel and Semtech.
Off-Chip Design Method for Improving Signal Integrity in Multi Branch Parallel interface of Non-Volatile Memory, authors from Samsung Electronics and Keysight Technologies.
PSIJ Based Integrated Power Integrity Design for HBM Using Reinforcement Learning: Beyond the Target Impedance,authors from KAIST and Missouri S&T.
Alongside the Best Paper Awards, the Early-Career Best Paper Award, first introduced in 2020, celebrates excellence amongst professionals within the first seven years of their career.
2025 Early-Career Best Paper Award Winners
Due to the very high ratings of their presentations, the following two papers received both Best Paper Awards and Early-Career Best Paper Awards.
A Parameter Extraction Method for Multi-Phase Buck Converters Based on Nonlinear Least Square Method, authors from Missouri University of Science and Technology and Google.
Post-FEC BER Analysis of 200 Gb/s Wireline Systems Using an FPGA Platform, authors from University of Toronto, Alphawave SEMI and Huawei Technologies Canada.
The full list of winning papers and contributing authors can be found at the DesignCon Best Papers Awards page.
DesignCon will return to the Santa Clara Convention Center, Feb. 24-26, 2026. For the latest news and information on the DesignCon 2025 program, please visit designcon.com.
About DesignCon
DesignCon is the world 's premier conference for chip, board, and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board, and systems designers in the country. DesignCon is organized by Informa, a leading B2B information services group and the largest B2B events and exhibitions organizer in the world. To learn more and for the latest news and information, visit www.informa.com. Design News and Battery Technology Online are the official publications of DesignCon. Connect with DesignCon and join the conversation on Facebook, LinkedIn, and X.
About Informa Markets Engineering
Informa Markets ' Engineering portfolio, a subsidiary of Informa plc (LON:INF), is the leading B2B event producer, publisher, and digital media business for the world 's $3-trillion advanced, technology-based manufacturing industry. Our print and electronic products deliver trusted information to the engineering market and leverage our proprietary 1.3-million-name database to connect suppliers with buyers and purchase influencers. We produce more than 50 events and conferences in a dozen countries, connecting manufacturing professionals from around the globe. The Engineering portfolio is organized by Informa, the world 's leading exhibitions organizer that brings a diverse range of specialist markets to life, unlocking opportunities and helping them to thrive 365 days of the year. For more information, please visit www.informamarkets.com.
Media Contact
Informa Markets Engineering
pr.ime@informa.com
SOURCE:INFORMA MARKETS - ENGINEERING
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